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authorDavid Lechner <[email protected]>2023-12-04 11:33:35 -0600
committerMark Brown <[email protected]>2023-12-06 14:19:36 +0000
commit07d33c2810bb5fe67747d11f76980ed68602e287 (patch)
treea6f75bb44fde74a6bc428538e6e78ca28f5b8d63 /scripts/generate_rust_analyzer.py
parent0db60d821e485a1c9b8080dbec1ba9871efb6a65 (diff)
spi: axi-spi-engine: add watchdog timer
If there is an issue with the AXI SPI Engine hardware a scheduled transfer might never be completed and spi_sync() will block forever. This due to the uninterruptible wait for completion waiting for the spi_finalize_current_message() that never comes. Add a watchdog timer that will abort a transfer 5 seconds after it has been started. This will potentially leave the hardware in a broken state but it allows software to recover and allow to better diagnose the underlying issue. Co-developed-by: Lars-Peter Clausen <[email protected]> Signed-off-by: Lars-Peter Clausen <[email protected]> Signed-off-by: David Lechner <[email protected]> Acked-by: Michael Hennerich <[email protected]> Acked-by: Nuno Sa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
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