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| author | Xianwei Zhao <[email protected]> | 2024-05-24 14:35:09 +0800 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2024-06-10 12:49:05 +0100 |
| commit | 022bd9c520d8f9dd51f29326eb369b8ec958f687 (patch) | |
| tree | 7004e001aa6f58018691c459cd466b0e188e5aa3 /scripts/generate_rust_analyzer.py | |
| parent | d4ea1d504d2701ba04412f98dc00d45a104c52ab (diff) | |
spi: meson-spicc: set SPI clock flag CLK_SET_RATE_PARENT
Add SPI clock flag CLK_SET_RATE_PARENT for using pclk as parent clock.
This gives SPI more flexibility in frequency selection.
Signed-off-by: Xianwei Zhao <[email protected]>
Signed-off-by: Sunny Luo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'scripts/generate_rust_analyzer.py')
0 files changed, 0 insertions, 0 deletions