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| author | S.j. Wang <[email protected]> | 2019-02-18 08:29:11 +0000 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2019-02-19 11:40:36 +0000 |
| commit | cc29ea007347f39f4c5a4d27b0b555955a0277f9 (patch) | |
| tree | 17471eb425a9722b171712ddc564a602412e8e2f /scripts/gen_compile_commands.py | |
| parent | d98afe1353b6dbd1527f3833da70d8525e6dbae3 (diff) | |
ASoC: fsl_esai: fix register setting issue in RIGHT_J mode
The ESAI_xCR_xWA is xCR's bit, not the xCCR's bit, driver set it to
wrong register, correct it.
Fixes 43d24e76b698 ("ASoC: fsl_esai: Add ESAI CPU DAI driver")
Cc: <[email protected]>
Signed-off-by: Shengjiu Wang <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Ackedy-by: Nicolin Chen <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'scripts/gen_compile_commands.py')
0 files changed, 0 insertions, 0 deletions