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| author | Christoph Hellwig <[email protected]> | 2019-07-03 09:54:44 -0700 |
|---|---|---|
| committer | Christoph Hellwig <[email protected]> | 2019-07-09 13:44:44 -0700 |
| commit | 7637de311bd2124b298a072852448b940d8a34b9 (patch) | |
| tree | af68ae72def48f858e4f961b382c8bd6b3021c48 /scripts/gen_compile_commands.py | |
| parent | bfac8e9f55cf62a000b643a0081488badbe92d96 (diff) | |
nvme-pci: limit max_hw_sectors based on the DMA max mapping size
When running a NVMe device that is attached to a addressing
challenged PCIe root port that requires bounce buffering, our
request sizes can easily overflow the swiotlb bounce buffer
size. Limit the maximum I/O size to the limit exposed by
the DMA mapping subsystem.
Signed-off-by: Christoph Hellwig <[email protected]>
Reported-by: Atish Patra <[email protected]>
Tested-by: Atish Patra <[email protected]>
Reviewed-by: Sagi Grimberg <[email protected]>
Diffstat (limited to 'scripts/gen_compile_commands.py')
0 files changed, 0 insertions, 0 deletions