drm/meson: Switch PLL to 5.94GHz base for 297Mhz pixel clock

On Amlogic G12A SoC, the 2,97GHz PLL frequency is not stable enough
to provide a correct 297MHz pixel clock, so switch the PLL base
frequency with a /2 OD when the 297MHz pixel clock is requested.

This solves the issue on G12A and also works fine on GXBB, GXL & GXM.

Signed-off-by: Neil Armstrong <[email protected]>
Tested-by: Jerome Brunet <[email protected]>
Reviewed-by: Jerome Brunet <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]

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