diff options
| author | Sergej Sawazki <[email protected]> | 2017-11-03 19:34:28 +0100 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2017-11-03 18:46:40 +0000 |
| commit | 81b3cc55afc3cde54df98f93fbd4704fab7cc0e0 (patch) | |
| tree | 575e3406f099ea7d4636146d37e871c94e0af9fa /scripts/gdb | |
| parent | eaf8abcfb21ecb5f6460d0505b03da4c3b7eee98 (diff) | |
ASoC: wm8741: Fix setting BCLK and LRCLK polarity
After checking the code and the datasheet, it seems like we are handling
the clock inversion (SND_SOC_DAIFMT_NB_IF and SND_SOC_DAIFMT_IB_IF) not
correctly.
>From the datasheet (Table 58):
R5 Format Control, BITS[5:4], [BCP:LRP]:
(0) 00 = normal BCLK, normal LRCLK
(1) 01 = normal BCLK, inverted LRCLK <-- Fix this
(2) 10 = inverted BCLK, normal LRCLK
(3) 11 = inverted BCLK, inverted LRCLK <-- Fix this
Signed-off-by: Sergej Sawazki <[email protected]>
Acked-by: Charles Keepax <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'scripts/gdb')
0 files changed, 0 insertions, 0 deletions