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authorDavid Lechner <[email protected]>2018-03-15 21:52:35 -0500
committerStephen Boyd <[email protected]>2018-03-20 10:16:26 -0700
commit58e1e2d2cd89a4aa77212eae64dd4824374e83f4 (patch)
tree746b90051104e52ab9cbda74bf989e6983178dfd /scripts/gdb
parent1e88a8d64f221208801bb279ee7452df0b6d609f (diff)
clk: davinci: cfgchip: Add TI DA8XX USB PHY clocks
This adds a new driver for the USB PHY clocks in the CFGCHIP2 syscon register on TI DA8XX-type SoCs. The USB0 (USB 2.0) PHY clock is an interesting case because it calls clk_enable() in a reentrant way. The USB 2.0 PSC only has to be enabled temporarily while we are locking the PLL, which takes place during the clk_enable() callback. Signed-off-by: David Lechner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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