diff options
| author | Dinh Nguyen <[email protected]> | 2019-08-14 10:30:14 -0500 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2019-08-14 09:23:21 -0700 |
| commit | c7ec75ea4d5316518adc87224e3cff47192579e7 (patch) | |
| tree | cf349df383621c280409c7788127b939ea6b90d8 /scripts/gdb/vmlinux-gdb.py | |
| parent | baf7b79e1ad79a41fafd8ab8597b9a96962d822d (diff) | |
clk: socfpga: stratix10: fix rate caclulationg for cnt_clks
Checking bypass_reg is incorrect for calculating the cnt_clk rates.
Instead we should be checking that there is a proper hardware register
that holds the clock divider.
Cc: [email protected]
Signed-off-by: Dinh Nguyen <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'scripts/gdb/vmlinux-gdb.py')
0 files changed, 0 insertions, 0 deletions