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| author | Huacai Chen <chenhuacai@loongson.cn> | 2022-07-20 18:51:31 +0800 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-07-20 12:09:21 +0100 |
| commit | b2d3e3354e2a0d0e912308618ea33d0337f405c3 (patch) | |
| tree | e0906b67599aaf9e75a87abf5b72289da19b4ee5 /scripts/gdb/vmlinux-gdb.py | |
| parent | dd281e1a1a937ee2f13bd0db5be78e5f5b811ca7 (diff) | |
irqchip: Add LoongArch CPU interrupt controller support
LoongArch CPUINTC stands for CSR.ECFG/CSR.ESTAT and related interrupt
controller that described in Section 7.4 of "LoongArch Reference Manual,
Vol 1". For more information please refer Documentation/loongarch/irq-
chip-model.rst.
LoongArch CPUINTC has 13 interrupt sources: SWI0~1, HWI0~7, IPI, TI
(Timer) and PCOV (PMC). IRQ mappings of HWI0~7 are configurable (can be
created from DT/ACPI), but IPI, TI (Timer) and PCOV (PMC) are hardcoded
bits, so we expose the fwnode_handle to map them, and get mapped irq
by irq_create_mapping when using them.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/1658314292-35346-13-git-send-email-lvjianmin@loongson.cn
Diffstat (limited to 'scripts/gdb/vmlinux-gdb.py')
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