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| author | Bharat Kumar Gogada <[email protected]> | 2022-07-05 16:26:45 +0530 |
|---|---|---|
| committer | Bjorn Helgaas <[email protected]> | 2022-07-22 14:12:00 -0500 |
| commit | 49f40703ca91c8428dd35e7331ae6c098e61b100 (patch) | |
| tree | 3fe5e407cc19e489aa3b01dd8483f6ef771598ee /scripts/gdb/vmlinux-gdb.py | |
| parent | f2906aa863381afb0015a9eb7fefad885d4e5a56 (diff) | |
dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
Xilinx Versal Premium series has CPM5 block which supports Root Port
functionality at Gen5 speed.
Add support for YAML schemas documentation for Versal CPM5 Root Port driver.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bharat Kumar Gogada <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Diffstat (limited to 'scripts/gdb/vmlinux-gdb.py')
0 files changed, 0 insertions, 0 deletions