clk: samsung: register exynos5420 apll/kpll configuration data

Register the PLL configuration data for APLL and KPLL on Exynos5420. This
configuration data table specifies PLL coefficients for supported PLL
clock speeds when a 24MHz clock is supplied as the input clock source
for these PLLs.

Cc: Tomasz Figa <[email protected]>
Signed-off-by: Thomas Abraham <[email protected]>
Reviewed-by: Amit Daniel Kachhap <[email protected]>
Tested-by: Arjun K.V <[email protected]>
Signed-off-by: Tomasz Figa <[email protected]>

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