diff options
| author | Alison Schofield <alison.schofield@intel.com> | 2024-07-02 22:29:52 -0700 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2024-07-11 16:29:43 -0700 |
| commit | 8f55ada796565ce801418bf579f31a6a522d0337 (patch) | |
| tree | 92d9dc7331f631b1aa611f66e5e59cc3f99b02c9 /scripts/gdb/linux/vfs.py | |
| parent | 82a3e3a235633aa0575fac9507d648dd80f3437f (diff) | |
cxl: Remove defunct code calculating host bridge target positions
The CXL Spec 3.1 Table 9-22 requires that the BIOS populate the CFMWS
target list in interleave target order. This means the calculations
the CXL driver added to determine positions when XOR math is in use,
along with the entire XOR vs Modulo call back setup is not needed.
A prior patch added a common method to verify positions.
Remove the now unused code related to the cxl_calc_hb_fn.
Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://patch.msgid.link/2e2c32a2d0f1007e920b58712d15edad2e48d857.1719980933.git.alison.schofield@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Diffstat (limited to 'scripts/gdb/linux/vfs.py')
0 files changed, 0 insertions, 0 deletions