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authorMarijn Suijten <[email protected]>2021-08-29 22:30:25 +0200
committerBjorn Andersson <[email protected]>2021-09-13 10:40:13 -0500
commitf1db21c315f4b4f8c3fbea56aac500673132d317 (patch)
treeab52d36722e8eda22a19d0fd699b3e55db2f78e1 /scripts/gdb/linux/utils.py
parentf5c03f131dae3f06d08464e6157dd461200f78d9 (diff)
ARM: dts: qcom: apq8064: Use 27MHz PXO clock as DSI PLL reference
The 28NM DSI PLL driver for msm8960 calculates with a 27MHz reference clock and should hence use PXO, not CXO which runs at 19.2MHz. Note that none of the DSI PHY/PLL drivers currently use this "ref" clock; they all rely on (sometimes inexistant) global clock names and usually function normally without a parent clock. This discrepancy will be corrected in a future patch, for which this change needs to be in place first. Fixes: 6969d1d9c615 ("ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY") Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Marijn Suijten <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
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