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| author | Andi Shyti <andi.shyti@linux.intel.com> | 2023-07-25 02:19:48 +0200 |
|---|---|---|
| committer | Andi Shyti <andi.shyti@linux.intel.com> | 2023-07-26 14:35:31 +0200 |
| commit | b70df82b428774875c7c56d3808102165891547c (patch) | |
| tree | 8b159df513ac18e2a535cac3b58c1d160943a2b3 /scripts/gdb/linux/utils.py | |
| parent | f2dcd21d5a22e13f2fbfe7ab65149038b93cf2ff (diff) | |
drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control and in the CS
Enable the CCS_FLUSH bit 13 in the control pipe for render and
compute engines in platforms starting from Meteor Lake (BSPEC
43904 and 47112).
For the copy engine add MI_FLUSH_DW_CCS (bit 16) in the command
streamer.
Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines")
Requires: 8da173db894a ("drm/i915/gt: Rename flags with bit_group_X according to the datasheet")
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Cc: <stable@vger.kernel.org> # v5.8+
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-6-andi.shyti@linux.intel.com
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions