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author | Artem Bityutskiy <artem.bityutskiy@linux.intel.com> | 2023-12-14 18:56:21 +0200 |
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committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2023-12-19 18:56:45 +0100 |
commit | ac89d11b93cc37c52dc38206c3eaffd4fa603f91 (patch) | |
tree | f717771c30b7a1e8964c0cea94259a4c005d3a6b /scripts/gdb/linux/utils.py | |
parent | eeae55ed9c0a74604a49789e36b7cdf0ee8bd69c (diff) |
intel_idle: add Grand Ridge SoC support
Add Intel Grand Ridge SoC C-states, which are C1, C1E, and C6S.
The Grand Ridge SoC is built with modules, each module includes 4 cores
(Crestmont microarchitecture). There is one L2 cache per module, shared
between the 4 cores.
There is no core C6 state, but there is C6S state, which has module
scope: when all 4 cores request C6S, the entire module (4 cores + L2
cache) enters the low power state.
Package C6 is not supported by Grand Ridge SoC.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions