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| author | Neil Armstrong <neil.armstrong@linaro.org> | 2023-10-12 11:01:28 +0200 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2023-10-16 09:38:22 -0700 |
| commit | 87e968672753191a71d4ec9b7585685a21768345 (patch) | |
| tree | 30187bbf248f0d1982a6dda12dbb3c34206b718e /scripts/gdb/linux/utils.py | |
| parent | 76191dc11ee8654f637aae2a083386f7278594d6 (diff) | |
drm/msm/dpu: add setup_clk_force_ctrl() op to sspp & wb
Starting from SM8550, the SSPP & WB clock controls are moved
the SSPP and WB register range, as it's called "VBIF_CLK_SPLIT"
downstream.
Implement setup_clk_force_ctrl() only starting from major version 9
which corresponds to SM8550 MDSS.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/562322/
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions