diff options
| author | Dave Jiang <[email protected]> | 2023-12-21 15:03:39 -0700 |
|---|---|---|
| committer | Dan Williams <[email protected]> | 2023-12-22 14:53:49 -0800 |
| commit | 4d07a05397c8c15c37c8c3abb7afaea1dcd2f0e7 (patch) | |
| tree | 593e045747cbd9c3a4bc6babe33bb1b3a32f40f8 /scripts/gdb/linux/utils.py | |
| parent | 790815902ec61ba1715fd67d3cb9036e13c942bc (diff) | |
cxl: Calculate and store PCI link latency for the downstream ports
The latency is calculated by dividing the flit size over the bandwidth. Add
support to retrieve the flit size for the CXL switch device and calculate
the latency of the PCIe link. Cache the latency number with cxl_dport.
Reviewed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Dave Jiang <[email protected]>
Link: https://lore.kernel.org/r/170319621931.2212653.6800240203604822886.stgit@djiang5-mobl3
Signed-off-by: Dan Williams <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions