diff options
| author | Hansen <[email protected]> | 2021-09-09 15:12:32 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2021-10-28 14:26:16 -0400 |
| commit | 3137f792c5bd68c799a9c3762fd37e428bbcf152 (patch) | |
| tree | 1c5ba79f9185aeddff3eedfd43ec163cc3372ba0 /scripts/gdb/linux/utils.py | |
| parent | a9a1ac44074ff8cab7d519277f93341e14557f83 (diff) | |
drm/amd/display: Set phy_mux_sel bit in dmub scratch register
[Why]
B0 has pipe mux for DIGC and DIGD which can be connected to PHYF/PHYG or
PHYC/PHY D.
[How]
Based on chip internal hardware revision id determine it is B0 and set
DMUB scratch register so DMUBFW can connect the display pipe is
connected correctly to the dig.
Cc: Wayne Lin <[email protected]>
Cc: Nicholas Kazlauskas <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Rodrigo Siqueira <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Hansen <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions