drm/amd/display: Cap certain DML values for Low Pix Clk on DCN2.1

[WHY]
In certain conditions with low pixel clock, some values in DML may go
past the max due to margining for latency hiding. This causes assertions
to get hit.

[HOW]
If the pixel clock is low and some values are high, cap it to the max.

Signed-off-by: Sung Lee <[email protected]>
Reviewed-by: Dmytro Laktyushkin <[email protected]>
Acked-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

0 files changed, 0 insertions, 0 deletions