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author | Tang Yuantian <[email protected]> | 2014-01-21 09:32:45 +0800 |
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committer | Mike Turquette <[email protected]> | 2014-03-19 17:04:14 -0700 |
commit | 00fa6e5d138a87f1b1bc8ae634c5f6fe513338c6 (patch) | |
tree | b4d3fb9d0e444ea484bd76bf2a27cd990157ae97 /scripts/gdb/linux/utils.py | |
parent | 141c71dd2c00ca7d807138ece55a17c61085c793 (diff) |
clk: mpc85xx: Update the driver to align to new clock bindings
The clock bindings for Freescale CoreNet platform are updated.
So, the driver needs to be updated accordingly.
The main changes include:
- Added a new node to present the input system clock
- Changed PLL and MUX's compatible string
Signed-off-by: Tang Yuantian <[email protected]>
Acked-by: Scott Wood <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions