soc/tegra: pmc: Add core power domain

NVIDIA Tegra SoCs have multiple power domains, each domain corresponds
to an external SoC power rail. Core power domain covers vast majority of
hardware blocks within a Tegra SoC. The voltage of a power domain should
be set to a level which satisfies all devices within the power domain.
Add support for the core power domain which controls voltage state of the
domain. This allows us to support system-wide DVFS on Tegra20-210 SoCs.
The PMC powergate domains now are sub-domains of the core domain, this
requires device-tree updating, older DTBs are unaffected and will continue
to work as before.

Tested-by: Peter Geis <[email protected]> # Ouya T30
Tested-by: Paul Fertser <[email protected]> # PAZ00 T20
Tested-by: Nicolas Chauvet <[email protected]> # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar <[email protected]> # Ouya T30
Signed-off-by: Dmitry Osipenko <[email protected]>
Reviewed-by: Ulf Hansson <[email protected]>
[[email protected]: squash lockdep class removal patch]
Signed-off-by: Thierry Reding <[email protected]>

0 files changed, 0 insertions, 0 deletions