diff options
| author | Peter Geis <[email protected]> | 2021-01-08 13:59:12 +0000 |
|---|---|---|
| committer | Takashi Iwai <[email protected]> | 2021-01-12 14:43:53 +0100 |
| commit | f4eccc7fea203cfb35205891eced1ab51836f362 (patch) | |
| tree | 37fe7d87a9cc3444455db0b666e72c36fb03c2c4 /scripts/gdb/linux/timerlist.py | |
| parent | 3e096a2112b7b407549020cf095e2a425f00fabb (diff) | |
clk: tegra30: Add hda clock default rates to clock driver
Current implementation defaults the hda clocks to clk_m. This causes hda
to run too slow to operate correctly. Fix this by defaulting to pll_p and
setting the frequency to the correct rate.
This matches upstream t124 and downstream t30.
Acked-by: Jon Hunter <[email protected]>
Tested-by: Ion Agorria <[email protected]>
Acked-by: Sameer Pujar <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Peter Geis <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Takashi Iwai <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/timerlist.py')
0 files changed, 0 insertions, 0 deletions