diff options
| author | Atish Patra <[email protected]> | 2020-03-17 18:11:43 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <[email protected]> | 2020-03-31 11:27:50 -0700 |
| commit | cfafe260137418d0265d0df3bb18dc494af2b43e (patch) | |
| tree | 50bde642415f253c2f4bf848fcb5441af43f2c79 /scripts/gdb/linux/timerlist.py | |
| parent | db5a79460315bd12dedee5f964cd72f3a534ecb2 (diff) | |
RISC-V: Add supported for ordered booting method using HSM
Currently, all harts have to jump Linux in RISC-V. This complicates the
multi-stage boot process as every transient stage also has to ensure all
harts enter to that stage and jump to Linux afterwards. It also obstructs
a clean Kexec implementation.
SBI HSM extension provides alternate solutions where only a single hart
need to boot and enter Linux. The booting hart can bring up secondary
harts one by one afterwards.
Add SBI HSM based cpu_ops that implements an ordered booting method in
RISC-V. This change is also backward compatible with older firmware not
implementing HSM extension. If a latest kernel is used with older
firmware, it will continue to use the default spinning booting method.
Signed-off-by: Atish Patra <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Signed-off-by: Palmer Dabbelt <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/timerlist.py')
0 files changed, 0 insertions, 0 deletions