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| author | Dustin L. Howett <dustin@howett.net> | 2024-04-02 19:47:13 -0500 |
|---|---|---|
| committer | Tzung-Bi Shih <tzungbi@kernel.org> | 2024-04-24 16:46:00 +0800 |
| commit | c8f460d991df93d87de01a96b783cad5a2da9616 (patch) | |
| tree | 1c8919a8d067dbce4a29fb2400e966d12c476fed /scripts/gdb/linux/timerlist.py | |
| parent | e4dbf9d65e421860af09e5cb44177416bb3afe80 (diff) | |
platform/chrome: cros_ec_lpc: add quirks for the Framework Laptop (AMD)
The original Framework Laptop 13 platform (Intel 11th, 12th, and 13th
Generation at this time) uses a Microchip embedded controller in a
standard configuration.
The newer devices in this product line--Framework Laptop 13 and 16 (AMD
Ryzen)--use a NPCX embedded controller. However, they deviate from the
configuration of ChromeOS platforms built with the NPCX EC.
* The MMIO region for EC memory begins at port 0xE00 rather than the
expected 0x900.
cros_ec_lpc's quirks system is used to address this issue.
Signed-off-by: Dustin L. Howett <dustin@howett.net>
Reviewed-by: Thomas Weißschuh <linux@weissschuh.net>
Tested-by: Thomas Weißschuh <linux@weissschuh.net>
Tested-by: Mario Limonciello <superm1@gmail.com>
Link: https://lore.kernel.org/r/20240403004713.130365-5-dustin@howett.net
Signed-off-by: Tzung-Bi Shih <tzungbi@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/timerlist.py')
0 files changed, 0 insertions, 0 deletions