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authorDinh Nguyen <[email protected]>2020-08-31 15:26:57 -0500
committerStephen Boyd <[email protected]>2020-09-22 12:54:41 -0700
commitb02cf0c4736c65c6667f396efaae6b5521e82abf (patch)
treea0fdac3b2e117b76b0a2d0ca8ead41f98cb50ed0 /scripts/gdb/linux/timerlist.py
parentf3bb0f796f5ffe32f0fbdce5b1b12eb85511158f (diff)
clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clk
The fixed divider the emac_ptp_free_clk should be 2, not 4. Fixes: 07afb8db7340 ("clk: socfpga: stratix10: add clock driver for Stratix10 platform") Cc: [email protected] Signed-off-by: Dinh Nguyen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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