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authorTaniya Das <[email protected]>2021-04-25 12:38:22 +0530
committerStephen Boyd <[email protected]>2021-05-25 20:36:21 -0700
commit7f891faf596ede96dd209b2257abf9df636b481f (patch)
treef17b731f339a3ccb3ec92e947efdb0a74948d2ac /scripts/gdb/linux/timerlist.py
parent6efb943b8616ec53a5e444193dccf1af9ad627b5 (diff)
clk: qcom: clk-rcg2: Add support for duty-cycle for RCG
The root clock generators with MND divider has the capability to support change in duty-cycle by updating the 'D'. Add the clock ops which would check all the boundary conditions and enable setting the desired duty-cycle as per the consumer. Signed-off-by: Taniya Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] [[email protected]: Remove _val everywhere] Signed-off-by: Stephen Boyd <[email protected]>
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