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| author | Srinivas Kandagatla <[email protected]> | 2021-06-24 10:21:53 +0100 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2021-06-24 19:29:53 +0100 |
| commit | 6a7f5bd6185e1c86256d5e52c3bb7a4d390d6e19 (patch) | |
| tree | 314eb98e36486ed4010771a646806d26d723a6a6 /scripts/gdb/linux/timerlist.py | |
| parent | 8cc802bd75fbf840635e7d4d48050bbcab4d938d (diff) | |
ASoC: qcom: lpass-cpu: mark IRQ_CLEAR register as volatile and readable
Currently IRQ_CLEAR register is marked as write-only, however using
regmap_update_bits on this register will have some side effects.
so mark IRQ_CLEAR register appropriately as readable and volatile.
Fixes: da0363f7bfd3 ("ASoC: qcom: Fix for DMA interrupt clear reg overwriting")
Reported-by: Marek Szyprowski <[email protected]>
Tested-by: Marek Szyprowski <[email protected]>
Tested-by: Srinivasa Rao Mandadapu <[email protected]>
Signed-off-by: Srinivas Kandagatla <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/timerlist.py')
0 files changed, 0 insertions, 0 deletions