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authorAlison Schofield <[email protected]>2021-06-17 16:12:15 -0700
committerDan Williams <[email protected]>2021-06-17 17:35:43 -0700
commitda6aafec3dca6132dd80a74a4d918ffd86c7ae35 (patch)
treea7c581cbe41f2faea4748ba58f6f75af086cb39c /scripts/gdb/linux/tasks.py
parent21083f51521fb0f60dbac591f175c3ed48435af4 (diff)
cxl/acpi: Add the Host Bridge base address to CXL port objects
The base address for the Host Bridge port component registers is located in the CXL Host Bridge Structure (CHBS) of the ACPI CXL Early Discovery Table (CEDT). Retrieve the CHBS for each Host Bridge (ACPI0016 device) and include that base address in the port object. Co-developed-by: Vishal Verma <[email protected]> Signed-off-by: Vishal Verma <[email protected]> Signed-off-by: Alison Schofield <[email protected]> Reviewed-by: Jonathan Cameron <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Link: https://lore.kernel.org/r/a475ce137b899bc7ae5ba9550b5f198cb29ccbfd.1623968958.git.alison.schofield@intel.com Signed-off-by: Dan Williams <[email protected]>
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