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| author | Kan Liang <[email protected]> | 2021-06-18 08:12:53 -0700 |
|---|---|---|
| committer | Peter Zijlstra <[email protected]> | 2021-06-23 18:30:55 +0200 |
| commit | d18216fafecf2a3a7c2b97086892269d6ab3cd5e (patch) | |
| tree | a06fe28ca2ea59a83187d9226113cf227176d7f6 /scripts/gdb/linux/tasks.py | |
| parent | ee72a94ea4a6d8fa304a506859cd07ecdc0cf5c4 (diff) | |
perf/x86/intel: Add more events requires FRONTEND MSR on Sapphire Rapids
On Sapphire Rapids, there are two more events 0x40ad and 0x04c2 which
rely on the FRONTEND MSR. If the FRONTEND MSR is not set correctly, the
count value is not correct.
Update intel_spr_extra_regs[] to support them.
Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by: Kan Liang <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Cc: [email protected]
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'scripts/gdb/linux/tasks.py')
0 files changed, 0 insertions, 0 deletions