clk: tegra: add fence_delay for clock registers

To ensure writes to clock registers have properly propagated through the
clock control logic and state machines, we need to ensure the writes have
been posted in the registers and wait for 1us after that.

Signed-off-by: Peter De Schrijver <[email protected]>
Reviewed-by: Jon Hunter <[email protected]>
Tested-by: Jon Hunter <[email protected]>
Tested-by: Hector Martin <[email protected]>
Tested-by: Andre Heider <[email protected]>
Tested-by: Mikko Perttunen <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>

0 files changed, 0 insertions, 0 deletions