diff options
| author | Ben Widawsky <[email protected]> | 2021-06-10 22:11:13 -0700 |
|---|---|---|
| committer | Dan Williams <[email protected]> | 2021-06-12 10:30:41 -0700 |
| commit | ba268647368844ed290e2f7b4da7a28cd12ee049 (patch) | |
| tree | 2a0c54fd82a3a5d0211e58ca0a9d3b831677fa43 /scripts/gdb/linux/tasks.py | |
| parent | 6423035fd26c1ecb72f90ecab909e9afa36942b8 (diff) | |
cxl/component_regs: Fix offset
The CXL.cache and CXL.mem registers begin after the CXL.io registers
which occupy the first 0x1000 bytes. The current code wasn't setting
this up properly for future users of the component registers. It was
correct for the probing code however.
Cc: Jonathan Cameron <[email protected]>
Cc: Ira Weiny <[email protected]>
Fixes: 08422378c4ad ("cxl/pci: Add HDM decoder capabilities")
Signed-off-by: Ben Widawsky <[email protected]>
Acked-by: Jonathan Cameron <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Dan Williams <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/tasks.py')
0 files changed, 0 insertions, 0 deletions