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author | Abel Vesa <[email protected]> | 2023-03-06 15:55:27 +0200 |
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committer | Bjorn Andersson <[email protected]> | 2023-03-06 19:42:04 -0800 |
commit | 77bf4b3ed42e31d29b255fcd6530fb7a1e217e89 (patch) | |
tree | c1a15d0957d03e9be3c8c9260ad0f7d9e8da0a10 /scripts/gdb/linux/tasks.py | |
parent | fe15c26ee26efa11741a7b632e9f23b01aca4cc6 (diff) |
soc: qcom: llcc: Fix slice configuration values for SC8280XP
The slice IDs for CVPFW, CPUSS1 and CPUWHT currently overflow the 32bit
LLCC config registers, which means it is writing beyond the upper limit
of the ATTR0_CFGn and ATTR1_CFGn range of registers. But the most obvious
impact is the fact that the mentioned slices do not get configured at all,
which will result in reduced performance. Fix that by using the slice ID
values taken from the latest LLCC SC table.
Fixes: ec69dfbdc426 ("soc: qcom: llcc: Add sc8180x and sc8280xp configurations")
Cc: [email protected] # 5.19+
Signed-off-by: Abel Vesa <[email protected]>
Tested-by: Juerg Haefliger <[email protected]>
Reviewed-by: Sai Prakash Ranjan <[email protected]>
Acked-by: Konrad Dybcio <[email protected]>
Reviewed-by: Johan Hovold <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'scripts/gdb/linux/tasks.py')
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