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author | Dan Williams <[email protected]> | 2021-02-16 20:09:50 -0800 |
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committer | Dan Williams <[email protected]> | 2021-02-16 20:36:38 -0800 |
commit | 4cdadfd5e0a70017fec735b7b6d7f2f731842dc6 (patch) | |
tree | 2799c35a3a590847b517271742eccde395655e6f /scripts/gdb/linux/tasks.py | |
parent | 1048ba83fb1c00cd24172e23e8263972f6b5d9ac (diff) |
cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints
The CXL.mem protocol allows a device to act as a provider of "System
RAM" and/or "Persistent Memory" that is fully coherent as if the memory
was attached to the typical CPU memory controller.
With the CXL-2.0 specification a PCI endpoint can implement a "Type-3"
device interface and give the operating system control over "Host
Managed Device Memory". See section 2.3 Type 3 CXL Device.
The memory range exported by the device may optionally be described by
the platform firmware memory map, or by infrastructure like LIBNVDIMM to
provision persistent memory capacity from one, or more, CXL.mem devices.
A pre-requisite for Linux-managed memory-capacity provisioning is this
cxl_mem driver that can speak the mailbox protocol defined in section
8.2.8.4 Mailbox Registers.
For now just land the initial driver boiler-plate and Documentation/
infrastructure.
Signed-off-by: Ben Widawsky <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Acked-by: David Rientjes <[email protected]> (v1)
Cc: Jonathan Corbet <[email protected]>
Link: https://www.computeexpresslink.org/download-the-specification
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Dan Williams <[email protected]>
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