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authorSerge Semin <[email protected]>2022-06-24 17:39:33 +0300
committerBjorn Helgaas <[email protected]>2022-08-01 15:01:25 -0500
commit14c4ad125cf94ba226556dd5cffbd00c6482c6bd (patch)
treea3e359ebf4f5dfabbee1f10fa11fa557f7e47c07 /scripts/gdb/linux/tasks.py
parent7659806aded90bbfdc8f31fc858bc661da5a2840 (diff)
PCI: dwc: Log link speed and width if it comes up
Printing just "link up" isn't very informative for PCI Express. Even if the link is up, bus performance can degrade to slower speeds or to narrower width than both Root Port and its partner is capable of. In that case it would be handy to know the link specifications as early as possible. If the link comes up, log the link speed (PCIe generation) and width. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
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