diff options
| author | JC Kuo <[email protected]> | 2021-01-20 15:34:02 +0800 |
|---|---|---|
| committer | Thierry Reding <[email protected]> | 2021-03-24 14:02:14 +0100 |
| commit | 0c7ea2b1c850756140fef03bed0fbaf0957f120a (patch) | |
| tree | a32863a42509224fa63a063185144946f80bb4b9 /scripts/gdb/linux/tasks.py | |
| parent | 54443ef6f5d10d9c6bb17f1dbeea7eb8d5c9a839 (diff) | |
clk: tegra: Don't enable PLLE HW sequencer at init
PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
power sequencers' output to enable/disable PLLE. PLLE hardware power
sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
are enabled.
Signed-off-by: JC Kuo <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/tasks.py')
0 files changed, 0 insertions, 0 deletions