diff options
| author | JC Kuo <jckuo@nvidia.com> | 2019-06-12 11:14:34 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-06-25 16:08:23 -0700 |
| commit | 0d34dfbf3023cf119b83f6470692c0b10c832495 (patch) | |
| tree | 43ff9067fbcbb7999a4750605d854d8aef693f30 /scripts/gdb/linux/symbols.py | |
| parent | a188339ca5a396acc588e5851ed7e19f66b0ebd9 (diff) | |
clk: tegra210: fix PLLU and PLLU_OUT1
Full-speed and low-speed USB devices do not work with Tegra210
platforms because of incorrect PLLU/PLLU_OUT1 clock settings.
When full-speed device is connected:
[ 14.059886] usb 1-3: new full-speed USB device number 2 using tegra-xusb
[ 14.196295] usb 1-3: device descriptor read/64, error -71
[ 14.436311] usb 1-3: device descriptor read/64, error -71
[ 14.675749] usb 1-3: new full-speed USB device number 3 using tegra-xusb
[ 14.812335] usb 1-3: device descriptor read/64, error -71
[ 15.052316] usb 1-3: device descriptor read/64, error -71
[ 15.164799] usb usb1-port3: attempt power cycle
When low-speed device is connected:
[ 37.610949] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
[ 38.557376] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
[ 38.564977] usb usb1-port3: attempt power cycle
This commit fixes the issue by:
1. initializing PLLU_OUT1 before initializing XUSB_FS_SRC clock
because PLLU_OUT1 is parent of XUSB_FS_SRC.
2. changing PLLU post-divider to /2 (DIVP=1) according to Technical
Reference Manual.
Fixes: e745f992cf4b ("clk: tegra: Rework pll_u")
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/symbols.py')
0 files changed, 0 insertions, 0 deletions