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authorMiquel Raynal <miquel.raynal@bootlin.com>2024-03-27 10:58:48 +0100
committerVinod Koul <vkoul@kernel.org>2024-04-07 17:08:45 +0530
commit5b9706bfc094314c600ab810a61208a7cbaa4cb3 (patch)
treec91f5bc0c085beba74e4884477dbce65a5d916fe /scripts/gdb/linux/stackdepot.py
parent244296cc3a155199a8b080d19e645d7d49081a38 (diff)
dmaengine: xilinx: xdma: Fix wrong offsets in the buffers addresses in dma descriptor
The addition of interleaved transfers slightly changed the way addresses inside DMA descriptors are derived, breaking cyclic transfers. Fixes: 3e184e64c2e5 ("dmaengine: xilinx: xdma: Prepare the introduction of interleaved DMA transfers") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com> Link: https://lore.kernel.org/r/20240327-digigram-xdma-fixes-v1-1-45f4a52c0283@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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