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| author | Arnd Bergmann <arnd@arndb.de> | 2024-04-09 16:30:24 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2024-04-09 16:30:25 +0200 |
| commit | 01a71af381a8002f37bac05f02a0aa84c00f4666 (patch) | |
| tree | 180a54eae70cb2cbf90a762b2f7520c7fb4448df /scripts/gdb/linux/stackdepot.py | |
| parent | e349017a7b5c15c5ecf9f088434c45772c323bba (diff) | |
| parent | c90847bcbfb65d0f1c48fcc73a2b3a2d4ceac6a1 (diff) | |
Merge tag 'riscv-soc-fixes-for-v6.9-rc3' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes
RISC-V SoC driver fixes for v6.9-rc3
A fix for the ccache driver which no longer probed after the PLIC driver
was converted to a platform driver. The JH7100 SoC depends on this
driver to provide cache management ops that must be registered with an
arch_initcall, so the ccache driver is partly converted to a platform
driver, registering only the cache management ops with the initcall and
the debug/edac register provision features of the driver as a platform
driver.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-soc-fixes-for-v6.9-rc3' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
cache: sifive_ccache: Partially convert to a platform driver
Link: https://lore.kernel.org/r/20240406-botch-disband-efc69b8236be@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'scripts/gdb/linux/stackdepot.py')
0 files changed, 0 insertions, 0 deletions