aboutsummaryrefslogtreecommitdiff
path: root/scripts/gdb/linux/slab.py
diff options
context:
space:
mode:
authorStephen Boyd <sboyd@kernel.org>2024-05-08 18:15:23 -0700
committerStephen Boyd <sboyd@kernel.org>2024-05-08 18:15:23 -0700
commitce6896285410bcfe90f8566ff0799e45e7820e52 (patch)
tree195359ac813195ba36490cd5923785e6e9e8d748 /scripts/gdb/linux/slab.py
parent4cece764965020c22cff7665b18a012006359095 (diff)
parent7c18b0a5aa46cc7e5d3a7ef3f9f8e3aa91bb780f (diff)
Merge tag 'samsung-clk-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung clk driver updates from Krzysztof Kozlowski: - Allow choice of manual or firmware-driven control over PLLs, needed to fully implement CPU clock controllers on Exynos850 - Correct PLL clock IDs on ExynosAutov9 - Propagate certain clock rates to allow setting proper SPI clock rates on Google GS101 - Add HSI0 and HSI2 clock controllers for Google GS101 - Mark certain Google GS101 clocks critical - Convert old S3C64xx clock controller bindings to DT schema * tag 'samsung-clk-6.10-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: gs101: drop unused HSI2 clock parent data clk: samsung: gs101: mark some apm UASC and XIU clocks critical clk: samsung: gs101: add support for cmu_hsi2 clk: samsung: gs101: add support for cmu_hsi0 dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit clk: samsung: gs101: propagate PERIC1 USI SPI clock rate clk: samsung: gs101: propagate PERIC0 USI SPI clock rate clk: samsung: exynosautov9: fix wrong pll clock id value dt-bindings: clock: samsung,s3c6400-clock: convert to DT Schema clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1 clk: samsung: Implement manual PLL control for ARM64 SoCs
Diffstat (limited to 'scripts/gdb/linux/slab.py')
0 files changed, 0 insertions, 0 deletions