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| author | Siarhei Volkau <lis8215@gmail.com> | 2024-04-30 18:45:58 +0300 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2024-05-03 14:22:38 +0200 |
| commit | 07e6a6d7f1d9fa4685003a195032698ba99577bb (patch) | |
| tree | b165364619eff3753f7f3a7c11b681a9fae67176 /scripts/gdb/linux/slab.py | |
| parent | bfe4ab93c80cc5689ab5a891e61013dfec48f56e (diff) | |
MIPS: Take in account load hazards for HI/LO restoring
MIPS CPUs usually have 1 to 4 cycles load hazards, thus doing load
and right after move to HI/LO will usually stall the pipeline for
significant amount of time. Let's take it into account and separate
loads and mthi/lo in instruction sequence.
The patch uses t6 and t7 registers as temporaries in addition to t8.
The patch tries to deal with SmartMIPS, but I know little about and
haven't tested it.
Changes in v2:
- clear separation of actions for SmartMIPS and pre-MIPSR6.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'scripts/gdb/linux/slab.py')
0 files changed, 0 insertions, 0 deletions