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| author | Xianwei Zhao <xianwei.zhao@amlogic.com> | 2024-05-22 16:27:26 +0800 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2024-06-04 10:38:16 +0200 |
| commit | 8a9a129dc565599a877ceac059ddd96ec81104eb (patch) | |
| tree | 63f22a2a5b4fefaba210e7bafd215b099cd0bd9b /scripts/gdb/linux/radixtree.py | |
| parent | d7583cde8c754cb4bd4262f26315407e21e42b3d (diff) | |
clk: meson: c3: add support for the C3 SoC PLL clock
Add the C3 PLL clock controller driver for the Amlogic C3 SoC family.
[jbrunet: fixed probe function name]
Co-developed-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240522082727.3029656-5-xianwei.zhao@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'scripts/gdb/linux/radixtree.py')
0 files changed, 0 insertions, 0 deletions