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author | Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> | 2023-11-14 21:22:52 +0900 |
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committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-11-20 09:17:15 +0100 |
commit | 5ab16198b431ca4885dbcc3433527fdf5b66be3c (patch) | |
tree | f0cc0ad5ef7ddf12dc88e51718e7190580cc9196 /scripts/gdb/linux/radixtree.py | |
parent | f154ef08ca637c26178cb7a5c8e7b75952a47ab1 (diff) |
clk: renesas: r8a779g0: Add PCIe clocks
Add the PCIe module clocks, which are used by the PCIe modules on the
Renesas R-Car V4H (R8A779G0) SoC. Note that the following descriptions
in the hardware manual Rev.0.81 about the PCIe module clocks are
incorrect:
9.2.1.7 Software Reset Register 6 (SRCR6)
9.2.1.12 Software Reset Register 11 (SRCR11)
9.2.3.7 Module Stop Control Register 6 (MSTPCR6)
Please refer to Figures 104.3[ab] instead.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231114122252.2266799-1-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/radixtree.py')
0 files changed, 0 insertions, 0 deletions