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| author | Cristian Ciocaltea <cristian.ciocaltea@collabora.com> | 2023-04-02 12:50:51 +0300 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2023-04-05 19:30:20 +0200 |
| commit | b46a22dea7530cf530a45c6b84c03300083b813d (patch) | |
| tree | 9ec1ce0d1592e61f42886a790e2c34b48c4bcc94 /scripts/gdb/linux/modules.py | |
| parent | 87810bda8a8472a9a106c6de34a032fb6a4b425b (diff) | |
arm64: dts: rockchip: Assign PLL_PPLL clock rate to 1.1 GHz on rk3588s
The clock rate for PLL_PPLL has been wrongly initialized to 100 MHz
instead of 1.1 GHz. Fix it.
Fixes: c9211fa2602b ("arm64: dts: rockchip: Add base DT for rk3588 SoC")
Reported-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20230402095054.384739-3-cristian.ciocaltea@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions