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| author | Sinthu Raja <[email protected]> | 2023-09-21 15:30:37 +0530 |
|---|---|---|
| committer | Vignesh Raghavendra <[email protected]> | 2023-10-05 20:44:41 +0530 |
| commit | b024d1a853b7bc8e2e01aa9a219d81a9df1a2ceb (patch) | |
| tree | e21039481290a9903fa098bf9961fb5452dfcb2e /scripts/gdb/linux/modules.py | |
| parent | c2e7258dbd451fff84fac2375aaec2f56f57f0b3 (diff) | |
arm64: dts: ti: Add USB Type C swap defines for J721S2 SoC
Lanes 0 and 2 of the J721S2 SerDes WIZ are reserved for USB type-C
lane swap. Update the macro definition for it.
Signed-off-by: Sinthu Raja <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vignesh Raghavendra <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions