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authorVince Bridgers <[email protected]>2015-02-12 10:47:33 -0600
committerDavid S. Miller <[email protected]>2015-02-19 15:23:42 -0500
commita923fc730fdbbf079eadfe2b9a1644971bd95793 (patch)
treedda5119ba0d2f3e2a9c0a724abc76518530ae6bf /scripts/gdb/linux/modules.py
parenta53c4bf7f27f043564f5bdace12405c54265cb66 (diff)
net: eth: altera: Change access ports to mdio for all xMII applications
Change use of Altera TSE's MDIO access from phy 0 registers to phy 1 registers. This allows support for GMII, MII, RGMII, and SGMII designs where the external PHY is always accesible through Altera TSE's MDIO phy 1 registers and Altera's PCS is accessible through MDIO phy 0 registers for SGMII applications. Signed-off-by: Vince Bridgers <[email protected]> Tested-by: Kai Lin Ng <[email protected]> Tested-by: Dalon Westergreen <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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