diff options
| author | Ludovic Desroches <[email protected]> | 2013-11-22 17:08:43 +0100 |
|---|---|---|
| committer | Nicolas Ferre <[email protected]> | 2013-12-02 14:14:42 +0100 |
| commit | 58e7b1d5826ac6a64b1101d8a70162bc084a7d1e (patch) | |
| tree | 133061595c50da263866003aca05cdccacc46576 /scripts/gdb/linux/modules.py | |
| parent | 6ce4eac1f600b34f2f7f58f9cd8f0503d79e42ae (diff) | |
ARM: at91: sama5d3: reduce TWI internal clock frequency
With some devices, transfer hangs during I2C frame transmission. This issue
disappears when reducing the internal frequency of the TWI IP. Even if it is
indicated that internal clock max frequency is 66MHz, it seems we have
oversampling on I2C signals making TWI believe that a transfer in progress
is done.
This fix has no impact on the I2C bus frequency.
Cc: <[email protected]> #3.10+
Signed-off-by: Ludovic Desroches <[email protected]>
Acked-by: Wolfram Sang <[email protected]>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions