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author | William Zhang <william.zhang@broadcom.com> | 2024-02-22 19:47:56 -0800 |
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committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2024-03-15 00:04:49 +0100 |
commit | 546e425991205f59281e160a0d0daed47b7ca9b3 (patch) | |
tree | a2c99e229df90d9e3a48af5eda5112b3059435c0 /scripts/gdb/linux/modules.py | |
parent | 198eef9f0646b9a15b60274f23b0e27f3387e690 (diff) |
mtd: rawnand: brcmnand: Add BCMBCA read data bus interface
The BCMBCA broadband SoC integrates the NAND controller differently than
STB, iProc and other SoCs. It has different endianness for NAND cache
data.
Add a SoC read data bus shim for BCMBCA to meet the specific SoC need
and performance improvement using the optimized memcpy function on NAND
cache memory.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: David Regan <dregan@broadcom.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20240223034758.13753-12-william.zhang@broadcom.com
Diffstat (limited to 'scripts/gdb/linux/modules.py')
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