diff options
| author | Stefan Agner <[email protected]> | 2020-12-07 18:58:02 +0100 |
|---|---|---|
| committer | Kevin Hilman <[email protected]> | 2020-12-07 11:12:49 -0800 |
| commit | 3d07c3b3a886fefd583c1b485b5e4e3c4e2da493 (patch) | |
| tree | c9fee80da61e23c9c89c75cc4b76175c51a87ff4 /scripts/gdb/linux/modules.py | |
| parent | 656ab1bdcd2b755dc161a9774201100d5bf74b8d (diff) | |
arm64: dts: meson: g12a: x96-max: fix PHY deassert timing requirements
According to the datasheet (Rev. 1.9) the RTL8211F requires at least
72ms "for internal circuits settling time" before accessing the PHY
registers. On similar boards with the same PHY this fixes an issue where
Ethernet link would not come up when using ip link set down/up.
Fixes: ed5e8f689154 ("arm64: dts: meson: g12a: x96-max: fix the Ethernet PHY reset line")
Reviewed-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Stefan Agner <[email protected]>
Signed-off-by: Kevin Hilman <[email protected]>
Link: https://lore.kernel.org/r/12506964ca5d5f936579a280ad0a7e7f9a0a2d4c.1607363522.git.stefan@agner.ch
Diffstat (limited to 'scripts/gdb/linux/modules.py')
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