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authorKonrad Dybcio <[email protected]>2023-03-16 15:12:58 +0100
committerBjorn Andersson <[email protected]>2023-04-04 20:18:31 -0700
commit2f51d9231485250c0e4cf4d7326c30109c553382 (patch)
treeaf241cc314bafb84475befe4e33446ff147a04bc /scripts/gdb/linux/modules.py
parent31cc61104f6894f686491dbbb5c8ece97b06e75d (diff)
arm64: dts: qcom: sm6375: Add CPUCP L3 node
Configure the L3 cache DVFS scaler within the CPUCP block to allow for dynamic frequency switching. Reviewed-by: Sibi Sankar <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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