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author | Udipto Goswami <[email protected]> | 2022-02-07 09:55:58 +0530 |
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committer | Greg Kroah-Hartman <[email protected]> | 2022-02-08 12:33:59 +0100 |
commit | 117b4e96c7f362eb6459543883fc07f77662472c (patch) | |
tree | 8ee8f6700ddd00b7a7feeb08906465f3c6e968a1 /scripts/gdb/linux/modules.py | |
parent | 5432184107cd0013761bdfa6cb6079527ef87b95 (diff) |
usb: dwc3: gadget: Prevent core from processing stale TRBs
With CPU re-ordering on write instructions, there might
be a chance that the HWO is set before the TRB is updated
with the new mapped buffer address.
And in the case where core is processing a list of TRBs
it is possible that it fetched the TRBs when the HWO is set
but before the buffer address is updated.
Prevent this by adding a memory barrier before the HWO
is updated to ensure that the core always process the
updated TRBs.
Fixes: f6bafc6a1c9d ("usb: dwc3: convert TRBs into bitshifts")
Cc: stable <[email protected]>
Reviewed-by: Pavankumar Kondeti <[email protected]>
Signed-off-by: Udipto Goswami <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions